An active-matrix driving method is a well-known conventional method for driving an image display device.
As illustrated in FIG. 36, an image display device driven by the active-matrix driving method includes pixel arrays, a scanning-signal-line driving circuit GD, and a data-signal-line driving circuit SD.
The pixel arrays include a number of scanning signal lines GL.sub.i, GL.sub.i+1 . . . and a number of signal lines SL.sub.i, SL.sub.i+1 . . . , arranged in rows and columns. Pixels are arranged between the scanning signal lines GL.sub.i, GL.sub.i+1 . . . and the signal lines SL.sub.i, SL.sub.i+1 . . . in a matrix.
The data-signal-line driving circuit SD samples an input video signal DATA in synchronism with a timing signal TIMING, and sends a video signal obtained by sampling to the data signal lines SL.sub.j, SL.sub.j+1 . . . after amplifying the obtained video signal if necessary.
The scanning-signal-line driving circuit GD successively selects a scanning signal line from the scanning signal lines GL.sub.i, GL.sub.i+1 . . . in synchronism with the timing signal so as to control the open/closed state of a switching signal element in the pixel. As a result, the data on the data signal lines SL.sub.j, SL.sub.j+1 is written and retained in the respective pixels.
If the image display device is a liquid crystal display device, as illustrated in FIG. 37, each pixel has a switching element SW such as MOSFET (electric field effect transistor) and a pixel capacitor (including a liquid crystal capacitor Cl, and an auxiliary capacitor Cs which is added if necessary).
When MOSFET is adopted as the switching element SW, the data signal line SL.sub.j is connected to one of the electrodes of the pixel capacitor through the drain and source of the MOSFET. The gate of the MOSFET is connected to the scanning signal line GL. The other electrode of the pixel capacitor is connected to a common electrode line which is common to all the pixels. The transmittance and the reflectance of liquid crystal is modulated by a voltage applied to the liquid crystal capacitor Cl to display an image.
In a conventional active-matrix liquid crystal display device, an amorphous silicon thin film on a transparent substrate is used as the switching element SW, and externally mounted ICs are used as the scanning-signal-line driving circuit GD and data-signal-line driving circuit SD.
With a recently reported technique for achieving a large-screen liquid crystal display device, pixel arrays and driving circuits can be monolithically formed on a polycrystalline silicon thin film. However, since a carrier mobility in a polycrystalline silicon thin-film transistor is smaller by a substantially one-order scale than that in a single crystal silicon transistor, the driving force is considerably decreased. If a driving circuit is constructed using a transistor of low performance, there is a possibility that data is not written.
The following description discusses in detail the data-signal-line driving circuit SD and the scanning-signal-line driving circuit GD.
There are two methods for driving the data signal line: one is a dot sequential driving method and the other is a line sequential driving method.
With the dot sequential driving method, as illustrated in FIG. 38, video signals input to a video signal input line SIG are written on data signal lines DL1, DL2 . . . by opening and closing analog switches AS in synchronism with output pulses from the respective stages in the shift register SR. Therefore, the time used for writing the video signals on the data signal lines DL1 and DL2 . . . is given by t.sub.He /n where t.sub.He is an effective horizontal scanning period (about 80% of a horizontal scanning period). Consequently, if the time constants (the product of capacitance and resistance) of the data signal lines DL1, DL2 . . . increase with an enlargement of the display size, the data may not be written completely, resulting in degraded display quality. The degradation of display quality tends to occur particularly when the analog switches AS are formed by transistors with small driving forces.
With the line sequential driving method, as illustrated in FIG. 39, video signals in the current horizontal scanning period are temporarily stored in a sampling capacitor C.sub.sa, and then the video signals are output to the data signal lines DL1, DL2 . . . through buffers (operational amplifiers) AMP in the next horizontal scanning period. Since the capacitance of the sampling capacitor C.sub.sa is usually smaller than that of each of the data signal lines DL1, DL2 . . ., writing of the video signals from a video input signal line SIG to the sampling capacitors C.sub.sa is carried out within a short time. Moreover, since the video signals are written to the data signal lines DL1, DL2 . . . having a larger load in the next horizontal scanning period, the data is completely written.
However, if the capacitance of the sampling capacitor C.sub.sa is increased so as to prevent a decrease in the charge retained in the sampling capacitor C.sub.sa due to leakage currents of the analog switches AS1 and AS2 and dividing charge in proportion to the capacitance when transmitted to the buffers AMP, the data can not be written accurately like in the case where the dot sequential driving method is used.
In order to solve the problems, as illustrated in FIG. 40, a data-signal-line driving circuit disclosed in Japanese Publication for Examined Patent Application No. 22917/1993 includes three shift registers SR1 to SR3 which are connected to (3n+1)th, (3n+2)th and (3n+3)th analog switches AS among the analog switches AS for sampling video signals, respectively. Here, n represents 0, 1, 2 . . . .
In this driving circuit, the three shift registers SR1 to SR3 are driven by clock signals CLK1 to CLK3 whose frequencies are reduced to one third of an original operational frequency and whose phases are slightly shifted relative to each other. With this structure, data is definitely written even when a polycrystalline silicon thin-film transistor of a small driving force is used.
With the above-mentioned conventional structure, however, a plurality of shift registers are necessary, and the area occupied by the data-signal-line driving circuit and the cost of the image display device are respectively increased. Additionally, this structure prevents a compact and light weight image display device. In particular, when a polycrystalline silicon thin-film transistor is used, it becomes difficult to use minute elements as compared with an IC which is formed on a single crystal silicon substrate, resulting in an increase in the area occupied by the data-signal-line driving circuit. Furthermore, an increase in the number of elements raises the rate of defective elements.
In recent years, the transistor characteristics of the polycrystalline silicon thin-film transistor has been improved by the development of a solid phase growth technique, a laser annealing technique or a technique for achieving fine polycrystalline silicon materials. With the development, even when one shift register is used, the possibility of obtaining a required operational frequency is increased. However, since the load of the analog switches is raised by increases in the size of display device and the number of gray levels, it becomes difficult to write video signals definitely even when a polycrystalline silicon thin film transistor of improved characteristics is used.
FIG. 41 shows a scanning circuit for a matrix display device driving circuit which is used for the data-signal-line driving circuit SD and the scanning-signal-line driving circuit GD and for controlling the timing of sampling of video signals or the timing of switching between ON and OFF of a signal to be applied to a scanning signal line.
The scanning circuit uses a master-slave shift register 905. The shift register 905 transmits a pulse signal sent from a start pulse signal line 902 in one direction sequentially to output signal lines 903-1, 903-2 . . . based on a signal from a clock signal line 901.
As illustrated in FIG. 42, signals synchronous with the rise of the signal of the clock signal line 901 are output to odd-numbered output signal lines 903-1, 903-3, and 903-5. On the other hand, signals synchronous with the fall of the signal of the clock signal line 901 are output to even-numbered output signal lines 903-2, 903-4, and 903-6.
The ON periods of signals on adjacent signal lines, for example, 903-1 and 903-2 overlap each other. Therefore, by calculating the AND of the signals on adjacent output signal lines among the output signal lines 903-1, 903-2 . . . in AND circuits 906-1, 906-2 . . . and outputting the result to the output signal lines 904-1, 904-2 . . . , pulse signals whose timing varies depending on the output signal lines 904-1, 904-2 . . . are obtained.
More specifically, as illustrated in FIG. 43, the shift register includes inverters connected in series. With this configuration, if a transistor constructing the shift register 905 has a defect, transistors located in stages after the defective transistor do not operate properly.
Assuming that the shift register 905 has ten transistors per output, each of the AND circuits 906-1, 906-2 . . . is formed by six transistors and that the probability of a transistor being non-defective is P(0.ltoreq.P.ltoreq.1), the probability that an output in Lth stage is correctly obtained is P.sup.10.times.(L+1)+6. At this time, the probability that outputs in the first stage to the Lth stage are correctly obtained is P.sup.16.times.L+10. Thus, when the number of stages in the shift register 905 increases, the probability that outputs are correctly obtained is lowered.
Moreover, if the display panel and the driving circuit are made as a single piece using the polycrystalline Si, the transistors are unlikely to operate properly due to different characteristics of the transistors and electrostatic breakdown, for example. As a result, the defect rate is considerably increased compared with that of ICs using single crystal.
Moreover, an image display device such as a three-panel projector requires a scanning circuit capable of performing bidirectional scanning. Namely, it is necessary to provide a shift register 905' for producing a bidirectional shift of pulse signal. In this case, since 16 transistors are necessary for each output stage, the probability that an output signal in the Lth stage in the scanning circuit is obtained is P.sup.16.times.(L+1)+6. Namely, the probability becomes lower than the probability obtained by a scanning circuit performing unidirectional scanning.
Japanese Publication for Examined Patent Application No. 13316/1990 discloses a method with which the defect rate is decreased by arranging the same circuits in parallel and disconnecting a circuit having a defect.
With this method, however, since the sizes of the circuits are increased by two times, the defective area also becomes twice larger. Moreover, since it is necessary to identify and disconnect a defective circuit, a long time is taken for inspecting and fixing the defective circuit, resulting in a lowering of the productivity.
On the other hand, Japanese Publication for Examined Patent Application No. 70157/1993 discloses a method with which a plurality of sampling switches are connected in series and sampling is performed without using a shift register by controlling the sampling switches to be ON and OFF by different signals. With this structure, it is possible to reduce the number of lines for connecting portions of a data-signal-line driving circuit which are integrally mounted on a display panel to portions thereof which are mounted separately from the display panel.
With this method, however, since a plurality of the sampling switches are connected in series, ON resistance is increased. In order to decrease the ON resistance, it is necessary to increase the sizes of transistors constituting the sampling switches. As a result, the size of the circuit is increased.
Moreover, since a great number of large transistors are connected to a signal line for controlling the sampling switches between ON and OFF, a delay is caused by the load of the transistors. In addition, since this method is applicable only to a circuit for driving data signal lines, it can not be used for a circuit for driving scanning signal lines.
Furthermore, for example, as shown in FIG. 45, when displaying images satisfying the XGA (extended graphic array) standard (horizontal scanning lines 1024.times.vertical scanning lines 768) on an image display device for displaying images satisfying the HDTV (high-definition television) standard (horizontal scanning lines 1840.times.vertical scanning lines 1035), there is a need to scan through right and left areas of the display panel where no image is displayed to an area where the next display data is to be displayed during the flyback period. It is thus necessary to scan at an increased operational frequency during the flyback period. Additionally, as illustrated in FIG. 46, when displaying images at a usual operational frequency, it is necessary to add a selector for selecting an input position of a start pulse for controlling an input position of a leading signal for performing displaying. Consequently, driving circuits are increased in size.
In order to solve such a problem, Paper TA9.1 of ISSCC 94 (1994 IEEE International Solid-State Circuits Conference) proposes a scanning circuit incorporating a decoder. With this method, however, since a large number of transistors are used, the circuit has an increased size.